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APIC ModeMany newer PCs are equipped with one or more Advanced Programmable Interrupt Controllers (APIC) which may be used as a replacement for the legacy i8259 master and slave interrupt controllers. APICs support more than 15 IRQs and the software overhead of handling interrupts is slightly smaller. APICs are mandatory for multiprocessor applications since only APICs are able to send interprocessor interrupts from one CPU to other CPUs. With single-processor applications, using APIC mode may be desirable to achieve better interrupt performance and less interrupt sharing. From an application point of view there is no difference between APIC mode and PIC (Programmable Interrupt Controller, the legacy i8259 chips) mode. Applications use the same interrupt handling API (see section Installing Hardware Interrupt Handlers). The APIC configuration of a PC is published by the BIOS through the MP Floating Pointer Structure as defined by Intel's MultiProcessor Specification Version 1.4 available at http://www.intel.com/design/archives/processors/pro/docs/242016.htm. RTTarget-32 requires this structure to be able to switch to APIC mode using RTMPSetAPICMode. Function RTMPDumpInfo can be used to dump the structure to a text file. If the BIOS does not publish this structure, or it contains errors, applications can install their own MP Floating Pointer Structure or generate one from ACPI tables. Please see section Custom MP Floating Pointer Structure, function RTMPACPITableCreate, and function RTMPSetAPICModeACPI for details. The x86 APIC infrastructure consists of one local APIC per logical CPU and one or more IOAPICs. Interrupt signals are connected to the IOAPIC and all APICs are connected among each other over a communication bus. When an external device activates its interrupt line, the signal arrives at an IOAPIC. The IOAPIC then sends a message to the local APIC of the CPU which should handle the interrupt. The selected local APIC then asserts the INT pin of the CPU. If RTMPSetAPICMode flag RT_APIC_LOWEST_INT_ROUTING has been specified, interrupts are sent to the CPU with the lowest interrupt load. In a multiprocessor system, several interrupts can be serviced simultaneously and in parallel. Applications which prefer to use APIC mode should enter APIC mode as soon as possible, and they should never switch back to PIC mode. This is important because function RTMPSetAPICMode may change the IRQ (and thus the interrupt vector) on which interrupts of PCI devices are delivered. If a driver has already installed an ISR for IRQ 5, for example, and then RTMPSetAPICMode changes the IRQ for that device to 21, the driver will no longer receive interrupts and fail. RTMPSetAPICMode flag RT_APIC_USE_LEGACY_MAP can be used to avoid this, but it locks out one important advantage of APIC mode: support for more than 15 IRQs.
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